Engineering of Reliable Embedded Systems

Using state-of-the art Time-Triggered architectures

Arabic, English
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This training has a focus on the use of state-of-the-art ‘Time-Triggered‘ (TT) architectures to support the development of software for safe and reliable embedded systems.

Who should attend?

This training covers the core techniques that are needed to design and implement TT software for use in safety-related embedded systems.

  • Taking this training will be of particular benefit to organizations that need to develop software for embedded systems in compliance with international safety standards, such as IEC 61508, ISO 26262, DO-178C, IEC 62304, ISO 13849, IEC 60335 and IEC 60730, up to ‘SIL 3’ / ‘ASIL D’ level or equivalent.
  • Taking this training will be of particular benefit to organizations that are ReliabiliTTy® licensees (or to organizations that are intending to become ReliabiliTTy licensees).


No knowledge of TT systems is assumed at the start of this training, but you may find it helpful to read the introductory chapter in the ERES2 book before you attend: this material can be downloaded from the ERES2 page (free of charge).

Software examples discussed during the course are in the ‘C’ language. Some familiarity with this programming language is assumed throughout the course. If your C is very rusty, you might like to take a look at the ‘Embedded C‘ book before you attend this training.

If you want to do further preparation, the videos for SafeTTy’s TTa training are freely available.


28 hours of lectures


  • Classroom:
    • Training slides in pdf format
    • Demo codes
    • A copy of the ‘ERES2’ book (paperback) for each participant
  • Self-learning
    • Training slides in pdf format
    • Demo codes
    • 2 months access to the training videos


  • Stm32Fxxx development board (if you do not have a board, you can run it on simulator)
  • CoolTerm (if simulator used, not needed)
  • Keil uVision MDK-ARM v 5.34 or higher

Examination option

The training option (detailed above) does not include the cost of taking the examinations on the SafeTTy Certified programme. Please contact SafeTTy for further information.


Course Content

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Task Design for Safe and Reliable Time-Triggered Systems
Modes, States / Multiple processors
Modelling Time-Triggered Systems
Monitoring Time-Triggered Systems
Lesson Content
0% Complete 0/1 Steps
Conventional RTOS vs. Time-Triggered Architecture in Safety-Related Designs
Open Discussion with Dr. Pont